1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and apparatus for preventing register data flow hazards in a simultaneous speculative threading (“SST”) processor.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
When a memory reference, such as a load operation, generates a cache miss, the subsequent access to level-two (L2) cache (or main memory) can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster.
Some processors are designed to support “simultaneous multi-threading” (SMT), wherein two or more “threads” of execution run simultaneously on a single processor core. On conventional processors that do not support SMT and can only handle a single execution thread, processor resources can sometimes sit idle (such as when the thread stalls awaiting a data return from memory). In contrast, an SMT processor that supports multiple threads can generally employ processor resources more efficiently. For example, in one type of SMT processor, a high-priority thread runs on the processor until it encounters a stall condition. At this point, the processor can deactivate the high-priority thread and can activate a low-priority thread. When the stall condition is ultimately resolved, the processor can inactivate the low-priority thread and can reactivate the high-priority thread. In this way, the processor avoids sitting idle while the high-priority thread is not performing useful work.
In an alternative scheme, processor designers have suggested using “speculative-execution” to avoid pipeline stalls associated with cache misses. Two such proposed speculative-execution modes are: (1) execute-ahead mode and (2) scout mode. Execute-ahead mode operates as follows. During normal execution, the system issues instructions for execution in program order. Upon encountering a data-dependent stall condition during execution of an instruction, the system generates a checkpoint that can be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of a data dependency are deferred, and wherein other non-deferred instructions are executed in program order.
When the unresolved data dependency is resolved during execute-ahead mode, the system enters a deferred-execution mode, wherein the system executes deferred instructions. If all of the deferred instructions are executed during this deferred-execution mode, the system returns to normal-execution mode to resume normal program execution from the point where the execute-ahead mode left off. Alternatively, if some deferred instructions were not executed during deferred-execution mode, the system returns to execute-ahead mode until the remaining unresolved data dependencies are resolved and the deferred instructions can be executed.
If the system encounters a non-data-dependent stall condition while executing in normal-execution mode or execute-ahead mode, the system moves into scout mode. In scout mode, instructions are speculatively executed to prefetch future loads and stores, but results are not committed to the architectural state of the processor. When the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal-execution mode) is finally resolved, the system uses the checkpoint to resume execution in normal-execution mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).
By allowing the processor to perform work during stall conditions, speculative-execution can significantly increase the amount of computational work the processor completes.
Unfortunately, existing processor designs that support the above-described type of speculative execution also have limitations. For example, existing processor designs that support speculative execution can only execute one thread of speculative execution at a time. Consequently, the processor may not achieve the maximum possible computational throughput.
Hence, what is needed is a method and apparatus which increases the amount of parallelism that can be achieved during speculative execution.